Showing results: 16 - 24 of 24 items found.
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ECP5 / ECP5-5G -
Lattice Semiconductor
*Up to 3.2 Gbps SERDES rate with ECP5, and up to 5 Gbps with ECP5-5G*Up to 4 channels per device in dual channel blocks for higher granularity*Enhanced DSP blocks provide 2x resource improvement for symmetrical filters*Single event upset (SEU) mitigation support*Programmable IO support for LVCMOS 33/25/18/15/12, XGMII, LVTTL, LVDS, Bus-LVDS, 7:1 LVDS, LVPECL and MIPI D-PHY input/output interfaces
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MachXO2 -
Lattice Semiconductor
*Up to 256 kbits of user Flash memory and up to 240 kbits sysMEM™ embedded block RAM*Up to 334 hot-socketable IOs that avoid excess leakage*Programmable through JTAG, SPI, I2C or Wishbone*TransFR feature allows in-field design update without interrupting equipment operation*Programmable sysIO™ buffer supports LVCMOS, LVTTL, PCI, LVDS, BLVDS, MLVDS, RSDS, LVPECL, SSTL, HSTL and more
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Lattice Propel Design Environment -
Lattice Semiconductor
Design Environment for Lattice FPGA-based Processor System Design - Lattice Propel is a complete set of graphical and command-line tools to create, analyze, compile, and debug both the hardware design of an FPGA-based processor system, and the software design for that processor system.
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Neural Network Compiler -
Lattice Semiconductor
Analyze networks for fit in the chosen number of engines and allocated memory. After compilation, simulate networks for functionality and performance prior to testing in hardware. Graphical display of networks supports analysis and understanding.
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Lattice Semiconductor
The product families on this page have been classified as "Mature". In most cases there is a newer technology product family that will better meet the needs of today's system logic designers. Designers working on new designs are strongly encouraged to evaluate the alternative product families listed in the "Use for New Designs" column. Unless a Mature Family has been formally superseded via our Product Change Notification (PCN) procedure Lattice will continue to support existing business for these Mature products. Certain of the products for which the PCN process has been completed have been transferred, as indicated in the table, to Rochester Electronics or Arrow Electronics. Please contact those companies for availability of the products indicated.
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Mach-NX -
Lattice Semiconductor
*Up to 8.4K LC of user logic, 2669 kbits of user flash memory and dual boot flash feature*Up to 379 programmable I/O supporting 1.2/1.5/1.8/2.5/3.3 I/O voltages*Secure enclave supports 384-bit cryptography, including SHA, HMAC, and ECC*Configuration of PFR and security functions through Lattice Propel simplifies developer experience*Highly reliable. Low power and 3X better SER performance to comparable CMOS technologies
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CertusPro-NX -
Lattice Semiconductor
*Up to 100K logic cells, 7.3 Mb of embedded memory blocks (EBR, LRAM), 156 18 x 18 multipliers, 299 programmable I/O, 8 SERDES supporting up to 10.3 Gbps per lane and supporting popular protocols (10 Gig Ethernet, PCIe Gen 3, DisplayPort, SLVS-EC and CoaXPress).*Packages as small as 9x9 mm, and in ball-pitch options of 0.5, 0.8 and 1.0 mm.*Power modes – User selectable Low Power vs. High Performance modes, enabled by FD-SOI programmable back-bias.*Design security – ECDSA bitstream authentication, coupled with robust AES-256 encryption.*Fast configuration – I/O configures in 4 ms, and full-device in under 30 ms in 100K LC device.
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MachXO3 -
Lattice Semiconductor
*Up to 9400 LUTs with up to 384 I/O pins*Instant-on 1 ms boot-up with background upgrade, Hitless I/O reconfigure and dual-boot error recovery*Available with 3.3/2.5 V core or low power 1.2 V core – including additional options on 9400 LUT devices*MachXO3LF includes programmable Flash and User Flash Memory (UFM)*Available in amazingly small (2.50 x 2.50 mm, 0.4 mm pitch) WLCSP packages and BGA packages with 0.50 mm and 0.80 mm pitch
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iCE40 LP/HX -
Lattice Semiconductor
*Available in three series with LUTs ranging from 384 to 7680: Low power (LP) and high performance (HX)*Integrated hard I2C and SPI cores that enable flexible device configuration through SPI*Match your preferred display to your application processor with interfaces such as RGB, 7:1 LVDS and MIPI DPI/DBI*Multi-source your image sensors by implementing flexible bridges supporting common interfaces such as HiSPi, subLVDS, LVDS and Parallel LVCMOS*Up to 128 kbits sysMEM™ Embedded Block RAM*Industry’s broadest range of 0.35 mm - 0.40 mm pitch BGAs fit in space-constrained applications