Agnisys, Inc.
Agnisys Inc. has established itself as a leading Electronic Design Automation (EDA) supplier of innovative software to solve complex design and verification problems for system development with certainty. Its products provide a common specification-driven development flow to describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) design, verification, firmware and validation. Based on patented technology and intuitive user interfaces, they increase productivity and efficiency while eliminating system design and verification errors. Founded in 2007, Agnisys is based in Lowell, Mass., with R&D centers in the United States and India.
- 1-855-837-4399
- (978) 349-6949
- sales@agnisys.com
- 75 Arlington St.
Suite 500
Boston, MA 02116
United States
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Applications
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product
Portable Sequence Generator for Verification, Firmware & Validation
ISequenceSpec
The complexity of modern SoC has raised the requirement for HW/SW co-simulation to catch the bugs from the early design stage. There is lack of common set of sequences which can be shared across the teams. ISepenceSpec helps design teams to generate the unified test and programming sequences in UVM and Firmware from the specification. ISequenceSpec uses the register information from importing the standard formats like IP-XACT, SystemRDL, XML. User can define the test sequences in a simple editor, and then generate the unified test sequences from verification to validation.
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product
UVM Register Generator
IDesignSpec™
IDesignSpec is an award winning product that helps IP/SoC design architects & engineers to create simple yet powerful specification in MS Word, Excel, Libre Office or plain text. The specification is content aware and any conflict in address is checked and highlighted in the specification itself. Any change done in the specification automatically gets translated into code.
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Design Verification Editor Checker for SV/UVM
DVinsight
DVinsight-Pro is a Integrated Development Environment (IDE) for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code. Design & Verification Engineers can create correct by construction DV code because DVinsight-Pro is a design verification editor checker that provides helpful insight into user code and ensures compliance with UVM best practices while adhering to established standards.
