Real Intent, Inc.
Real Intent is the leading provider of EDA software to accelerate Early Functional Verification and Advanced Sign-off of digital designs. It provides comprehensive clock-domain crossing verification, advanced RTL analysis and sign-off solutions to eliminate complex failure modes of SoCs. The Meridian and Ascent product families lead the market in performance, capacity, accuracy and completeness.
- 408-830-0700
- 408-737-1962
- info@realintent.com
- 990 Almanor Avenue, Suite 220
Sunnyvale, CA 94085
United States
Filter Results By:
Products
Applications
-
product
Clock Domain Crossing Sign-off Solution
Meridian CDC
Meridian CDC is the fastest, highest capacity and most precise CDC solution in the market. It performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC, or FPGA devices are received reliably. Meridian CDC is the only solution that enables all aspects of CDC sign-off for giga-gate SoC designs.
-
product
RTL Lint Analyzer and Rule Checker
Ascent Lint
Ascent Lint is a state-of-the-art RTL linter and rule checker for full-chip SoC analysis. Designed from the bottom-up to deliver the highest performance, capacity and low-noise reporting, it is the best-in-class HDL linter available today with a comprehensive set of syntax and semantic checks.
-
product
Advanced Multimode Sign-off Verification
Verix PhyCDC
Verix PhyCDC is the only solution that delivers precise netlist CDC sign-off including glitch checking. RTL CDC sign-off assumptions may become invalid because of logic synthesis and power optimizations. Verix PhyCDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains are CDC-safe at the gate level. Complementing Real Intent’s Verix CDC solution that provides comprehensive analysis for RTL sign-off, Verix PhyCDC delivers the most advanced netlist sign-off for giga-gate designs.
-
product
Multimode Intent Driven Clock Domain Crossing Sign-off of SoC Designs
Verix CDC
Verix product family initially offers Verix CDC, which provides one-step analysis and debug of all operating modes in an IC, and boosts productivity for SoC and FPGA design teams. Verix CDC, with its proprietary static intent verification technology, is the most precise and lowest-noise solution in the industry for multimode CDC analysis.
-
product
X-Design and Verification System
Ascent XV
The Ascent X-design and verification system (XV) prevents, detects and isolates issues caused by the propagation of unknowns (‘Xs’) in RTL designs, including Xs that occur during power-on initialization and switching between power modes. Early sign-off of X issues eliminates costly, painful gate-level debug, and prevents hidden functional bugs from slipping through to silicon.
-
product
Correction in Gate-level Simulations Software
Verix SimFix
Verix X-Pessimism correction system (SimFix) enables accurate gate-level simulations (GLS) that are necessary for a thorough verification sign-off. Inaccurate simulation is caused by the propagation of pessimistic unknowns (e.g. X’s) in netlist designs. SimFix uses mathematical methods to identify conditions under which pessimism can occur, and to determine the correct value when those conditions occur. It then generates auxiliary SimPortal files that, when used in simulation, will detect and correct pessimism so that the simulation accurately models real hardware. Without SimFix, GLS verification is compromised by inaccurate random initialization or costly synthesis switches, neither of which is foolproof and often still requires long and laborious gate-level debug.
