Test Insight Ltd.
Test Insight is an intelligent software house developing solutions for design and test closed loop, and leads the standard in software tools to ATE industry.
- 972-3-7517383
- 972-3-6122128
- info@testinsight.com
- 6 Hachilazon St.
Ramat Gan, 52522
Israel
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product
Content based revision compare of Test Programs
Test program Comparator
TP-C is part of the new test program life cycle solutions from TestInsightAddress concerns such as - Why does my test program yield differently in two sites ? Is it really the same program ? What is different in a given test program revision ?
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Conversion Tools
Tester Data Link
VCD/eVCD to tester conversion (via STIL)WGL/TDL to tester conversion (via STIL)Most flexibility to handle complex devices functionality Support protocol definitionUtilize advanced tester features (Such as Xmode, concurrent test etc’… )High Performance Fast run time
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Direct conversion from cycle driven simulation data
Test program generator
Direct conversion from cycle driven simulation data (ATPG scan patterns) (WGL/TDL/STIL) to tester. TDL/WGL/STIL to tester conversion Supports STIL ext 0,1,2 constructs Easy to use and cost effective conversion solution Optimize tester resources usage Supports advanced tester features (Such as Xmode, Multi-port etc’) Compress and minimize vectors count Allow direct tester binary patterns creation
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Test Program Management
TP-M
TP-M utilizes TestInsight unique capability to read and analyze a whole test program from flow to every test pattern, timings, levels etc.
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Wave display utility
GUI
GUI allowing users to view and analyze test vectors in all common formats (VCD/EVCD/WGL/STIL).
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Emulate Test in simulation
STIL-VT
Emulate test patterns in simulation environment with DUT simulation model. The simulation allows pre-silicon debug of test patterns. Reads the intermediate STIL format of tester patterns and creates a Verilog /VHDL simulation test bench. (A sub-set of Virtual tester solution)
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Pattern Conversion
Wave Wizard
Wave Wizard generates a test program according to device spec. It avoids the inherent problems that exist when trying to force an event-driven simulation into a constrained ATE test program, by considering device perspective.
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Virtual tester
Emulate tester patterns in simulation environment with DUT simulation model. The simulation allows pre-silicon debug of test programs. Reads the actual ATE program and creates a Verilog /VHDL simulation test bench.
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Link simulation to ATE conversion
VCD2ATE
VCD2ATECost effective link simulation to ATE conversionDirect conversion from event driven design simulation dump (VCD/EVCD) to specific tester program files. VCD/eVCD to tester conversion Simple and cost effective conversion solution Simple cycle definition in excel High Performance Fast run time Handles very large files >6Gb
