OneSpin Solutions GmbH
Our software tools help the world's most innovative companies to create bug-free digital integrated circuits. We target the most difficult verification challenges and provide focused, complete (product & service) solutions to make electronics reliable.
- 408 734 1900
- info@onespin.com
- 4820 Harwood Road
#250
San Jose, CA 95124
United States
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product
360 DV-Verify
Unified, coverage-driven assertion-based verification, including a full automated apps library.
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ISO 26262 FMEDA Solution
OneSpin automates the FMEDA steps through a series of safety apps integrated in a comprehensive, interoperable flow that leverages structural analysis, formal proofs, and expert knowledge. The apps can be applied at chip level, and support both RTL and gate-level design models. Crucially, the OneSpin FMEDA flow does not require a test bench, reduce or eliminates slow and effort-intensive fault simulation, and quickly detects shortcomings in the safety architecture.
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360 EC-FPGA
Functional correctness of FPGA synthesis from RTL code to final netlist. Systematic design errors, introduced by automated design refinement tools, such as synthesis, can be hard to detect, and damaging if they make it into the final device. Formal equivalence checking has been used for ASIC design flows for many years. As FPGAs become bigger and critical system components, exhaustively verifying the functional equivalence of Register Transfer Level (RTL) code to synthesized netlists and the final placed & routed FPGA designs is mandatory.
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360 EC-RTL
During a typical development process, there are many occasions where a change needs to be made to a block, which must then be retested to ensure functional equivalence. For example, once a block has been proven to operate correctly, a designer may wish to optimize some section, maybe to improve the coding style, reduce the gate count or streamline operation. Today, an engineer must execute an entire simulation regression run to verify each change. This often requires a lot of time and may also need additional stimulus, with no guarantee that an exhaustive functional check will be performed.
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360 DV-Inspect
Automatic and exhaustive analysis of a code base for classic implementation problems.
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360 EC-ASIC
ASIC synthesis verification from RTL code to final netlist.Systematic design errors, introduced by automated design refinement tools, such as ASIC synthesis, can be hard to detect, and damaging if they make it into the final device. Formal Equivalency Checking (EC) has become a standard part of the ASIC development flow, replacing almost all gate level simulation with a rigorous consistency check between pre- and post-synthesized code.
