Verific Design Automation, Inc.
verific-teamVerific Design Automation, with offices in Kolkata, India and Alameda, CA, was founded in 1999 by EDA industry veteran Rob Dekker. Prior to founding Verific, Dekker was a software developer, manager and director at Exemplar Logic. As a leading provider of SystemVerilog, VHDL, and UPF front-ends, Verific’s software is used worldwide in synthesis, simulation, formal verification, emulation, debugging, virtual prototyping and design-for-test applications, which combined have shipped over 60,000 copies.
- (510) 522 1555
- (510) 522 1553
- info@verific.com
- 1516 Oak Street, suite 115
Alameda, CA 94501
United States
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SystemVerilog, VHDL & Unified Power Format (UPF) Parser Platforms
Verific Design Automation, Inc.
SystemVerilog (which includes Verilog 2001) and VHDL are parsed and processed in two steps, analysis and elaboration. Mixed VHDL and SystemVerilog compilation is fully supported. UPF is processed in a single step, analysis.
