Transistor-Level Defect Simulator

Tessent DefectSim - Mentor Graphics Corp. (Mentor)

Tessent DefectSim is a transistor-level defect simulator for analog, mixed-signal (AMS), and non-scan digital circuits. It measures defect coverage and defect tolerance. Tessent DefectSim is perfect for both high-volume and high-reliability ICs. Tessent DefectSim replaces manual test coverage assessment in AMS circuits needed to meet quality standards such as ISO 26262 and provides objective data to guide improvements in DFT. Tessent DefectSim dramatically reduces SPICE simulation time compared to simulating every potential defect.