FPGA Testing

Silicon Turnkey Solution, Inc. (STS)

The secret to our success in the FPGA testing field is the STS hammer file, a proprietary test methodology based on our experience testing thousands of unique FPGA designs. The hammer file is designed to program the FPGA to its maximum combination and block configuration and then tests the completely programmed FPGA for full dynamic, DC and at-speed AC performance. Power and transient tests are also conducted under worst-case populated configurations. Application-specific usage configurations are also used to assist in generating the worst-case electrical specification limits at worst-case environmental use.