Low Power FPGA Featuring Hardened MIPI D-PHY, LVDS, SLVS, SubLVDS, & Open LDI Bridging

Low Power FPGA Featuring Hardened MIPI D-PHY, LVDS, SLVS, SubLVDS, & Open LDI Bridging

*Two 4-lane MIPI D-PHY transceivers at 6 Gbps per PHY
*15 programmable source synchronous I/O pairs for camera and display interfacing
*Available in amazingly small 2.46 mm x 2.46 mm WLCSP packages and BGA packages with 0.4 mm, 0.5 mm and 0.65 mm pitch

Get Help