FPGA Mezzanine Card

FPGA Mezzanine Card

The FMC165 provides two 14-bit analog-to-digital (A/D) channels supporting RF sampling at 2.6 GSPS and one 14-bit digital-to-analog (D/A) channel with sampling rates up to 5.2 GSPS (2.6 GSPS direct RF synthesis). The converters are clocked by either an internal clock source (optionally locked to an external reference) or an externally supplied sample clock. In addition, a trigger input for customized sampling control is available to users.

Subcomponents

  • SSMB Jack coax (Female): Quantity: 1

  • SSMB Jack coax (Female): Quantity: 1

  • SSMB Jack coax (Female): Quantity: 1

  • SSMB Jack coax (Female): Quantity: 1

  • SSMB Jack coax (Female): Quantity: 1

  • SSMB Jack coax (Female): Quantity: 1

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