CoreCommander
While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-existent BSRs. CoreCommander Micro uses the on-chip debug mode of processors to access ports and embedded peripheral controllers to promote ''kernel-centric'' testing. Similarly, in the case of today's Field Programmable Gate Arrays (FPGAs) test engineers can ''bridge'' from the JTAG interface to the resources of the gate array itself. Our CoreCommander FPGA product implements a translatorinterface that allows our JTAG hardware to control embedded IP cores via a variety of bus interfaces (e.g. Wishbone Avalon etc.).
