Advanced Node Solution
A major new challenge at 20nm/14nm is the requirement for extra masks (double patterning technology, or DPT) to make existing lithography work at this advanced node. Read 20 questions on 20nm - a Q&A document. Escalating data volume and denser, more complex chips are testing the limits of traditional routing architectures. Even the slightest perturbations in the design flow can cause dramatic swings in design integrity. Engineers face a predictability crisis riddled with silicon failures, performance degradation, and prolonged design schedules. And new process and design innovationshigh-k metal gate, SOI, 3D-IC packagingare intensifying the pressures of adoption and rapid deployment.
