Parallel Simulation Engine

RocketSim - Cadence Design Systems

Complementing compiled-code simulators, Cadence® RocketSim™ parallel simulation engine eliminates functional verification bottlenecks by speeding up simulation using commonly available multi-core servers. The engine is proven for register-transfer level (RTL) system on chip (SoC), gate-level functional simulation, and gate-level design for test (DFT) simulation in numerous marquee systems and semiconductor companies in the mobile, server, and graphics domains. Ever-growing chip density and complexity slow down simulation, making functional verification a severe bottleneck. As a result, chip design projects miss their time-to-market targets, or designers end up taping out early with less confidence. RocketSim parallel simulation engine solves the bottleneck common in existing compiled-code simulators by offloading the time-consuming calculations to an ultrafast multi-core engine.