DDR Bus Simulator

W2309EP - Keysight Technologies

The W2309EP DDR Bus Simulator quickly generates accurate bit-error-rate (BER) contours, masks, and margins between the two, for the DDR memory bus specification published by JEDEC. The simulator achieves this by use of statistical simulation, meaning no lengthy and time-consuming bit pattern is needed. Instead, it constructs the eye diagram from the transmitter, channel, and receiver impulse responses, and from the stochastic properties of a conceptually infinite non-repeating bit pattern. In doing so it avoids the pitfalls associated with precarious dual-Dirac extrapolation of a limited bit pattern from either SPICE-like simulation or from convolutional channel simulation.