Showing results: 1 - 5 of 5 items found.
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DFT- PRO Plus -
Syntest Technologies
DFT-PRO Plus offers an integrated DFT solution covering scan synthesis and ATPG, memory Built-In Self-Test (BIST) synthesis and boundaryscan (BSD) synthesis. The corresponding tools generate RTL blocks that fit seamlessly into an existing synthesis flow
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NetUSB II™ -
Corelis, Inc.
Boundary-scan has proven itself time and again to be a truly versatile interface for structural test, embedded functional test, built-in self-test (BIST), software debug, and in-system programming. Supporting such diverse applications requires a controller with high performance specifications and diverse features.
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Averna
Smart, swappable fixtures and flexible test bedsMulti-site setups, including multi-threadingLong-wire, short wire, and wirelessBed-of-nails for in-circuit testing (ICT)RF, high-speed digital, and thermal designsSolidWorks design expertise and global manufacturing (e.g., US, Mexico, China)Multiple options for mass interconnects (VPC, MAC Panel) and harnessesBuilt-in self-test (BIST) fixtures and calibration tools
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ScanTAP 4 & 8 -
Corelis, Inc.
Boundary-scan has proven itself time and again to be a truly versatile interface for structural test, embedded functional test, built-in self-test (BIST), software debug, and in-system programming. Supporting such diverse applications requires equipment with high-performance specifications and extended features.Corelis ScanTAP pods are designed for use with PCI-1149.1/Turbo and PCIe-1149.1 high-speed JTAG controllers. Featuring 4 & 8 independent Test Access Ports (TAPs), up to 80 MHz clock rates, and advanced TAP capabilities such as analog voltage measurement, the ScanTAP family of intelligent pods is the ideal JTAG interface for high-performance environments.
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T5230 -
Advantest Corp.
T5230 memory test system for NAND/NVM devices adopts a combined array architecture to achieve best-in-class cost-of-test performance for wafer test, including wafer-level burn-in (WLBI) and built-in self-test (BIST). The system can perform on-wafer test of 1,024 memory devices per test head in parallel, delivering high productivity and enabling floor space savings of up to 86%. Multiple test cells are connected per system controller in the T5230, allowing independent wafer test of each test cell. The test cells can be stored in a general multi-wafer prober while minimizing the test cell floor space, and the tester can be docked with probers in both linear and multi-stack configurations. For functional tests at a maximum test rate of 125MHz/250Mbps, the T5230 assures high timing accuracy, repeatability, and failure detection capability.
