Showing results: 886 - 888 of 888 items found.
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Torontech Group
Optical fiber consists of a core and a cladding layer, selected for total internal reflection due to the difference in the refractive index between the two. In practical fibers, the cladding is usually coated with a layer of acrylate polymer or polyimide. This coating protects the fiber from damage but does not contribute to its optical waveguide properties. Individual coated fibers then have a tough resin buffer layer and/or core tube(s) extruded around them to form the cable core. Several layers of protective sheathing, depending on the application, are added to form the cable. Rigid fiber assemblies sometimes put light-absorbing ("dark") glass between the fibers, to prevent light that leaks out of one fiber from entering another. This reduces cross-talk between the fibers, or reduces flare in fiber bundle imaging applications Optical fibers are very strong, but the strength is drastically reduced by unavoidable microscopic surface flaws inherent in the manufacturing process. The initial fiber strength, as well as its change with time, must be considered relative to the stress imposed on the fiber during handling, cabling, and installation for a given set of environmental conditions. There are three basic scenarios that can lead to strength degradation and failure by inducing flaw growth: dynamic fatigue, static fatigues, and zero-stress aging.
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ProcVision -
Gidel
Gidel’s Vision Pro Development Kit is an optimal solution for developing,validating, demonstrating and evaluating Image Processing (IP) andpipeline designs on FPGA.The suite is designed to provide a complete and convenient envelop enablingthe developer to focus strictly on the proprietary image processingdesign. The entire Vision Pro flow is within a single FPGA, independentof the final target application(s). The Vision Pro flow is composedof a pipeline that streams simulated data to the user image processingdesign under test (DUT) and then captures the design’s output streamfor displaying, storing, analysis and/or co-processing on host software.The entire process is performed on a single FPGA without the need foradditional peripheral connectivity or tools.Vision Pro suite is plug-and-play enabling the developer to begin at oncethe IP design development and validation. A simple design example providesthe developer immediate hands-on familiarization with the systemflow and supporting tools. The final design can be ported to any IntelFPGA device or other vendors’ devices (FPGA or ASIC) by replacing basiclibraries. To significantly reduce compilation time, initial design developmentmay be on a small FPGA device and later compiled for the targetdevice(s). The target implementation may use any FPGA board. For a fullImaging/Vision system solution, Gidel offers a number of off-the-shelfgrabbers and FPGA accelerators that are designed to utilize these imageprocessing blocks and Gidel Imaging Library (GIL).
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