Cadence Design Systems

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Electrical DFM analysis and optimization

LDE Electrical Analyzer

Cadence Design Systems

LDE Electrical Analyzer - Cadence Design Systems

The Cadence LDE Electrical Analyzer helps designers identify, analyze, and minimize the effect of parametric issues associated with manufacturing variability to improve design performance.

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3D-IC Solution

Cadence Design Systems

Cadence Design Systems

Consumer demand for increased bandwidth and low power in smaller form factor has forced design teams to pursue design and manufacturing alternatives to single system-on-chip (SoC) approaches. Moving to advanced geometries like 20nm/14nm is a natural progression; however, it has its own cost, yield, manufacturing, and IP reuse challenges. This has given way to a viable alternative of exploring the third dimension in design and manufacturing: 3D-ICs with through-silicon vias (TSVs).

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Low-Power Solution

Cadence Design Systems

Cadence Design Systems

Power consumption affects the designer's ability to differentiate a product based on features, cost, performance, time to market, and even reliability. For mobile equipment, the explosion of applications leads to skyrocketing performance demands, in turn requiring innovative energy management. For data centers, where cooling represents a large proportion of overhead, power density management is critical to reduce cooling costs and increase reliability. Finally, at advanced process nodes, leakage is a critical issue, turning nearly all designs into advanced low-power designs.

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Advanced Node Solution

Cadence Design Systems

Cadence Design Systems

A major new challenge at 20nm/14nm is the requirement for extra masks (double patterning technology, or DPT) to make existing lithography work at this advanced node. Read 20 questions on 20nm - a Q&A document. Escalating data volume and denser, more complex chips are testing the limits of traditional routing architectures. Even the slightest perturbations in the design flow can cause dramatic swings in design integrity. Engineers face a predictability crisis riddled with silicon failures, performance degradation, and prolonged design schedules. And new process and design innovationshigh-k metal gate, SOI, 3D-IC packagingare intensifying the pressures of adoption and rapid deployment.

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Cloud-Ready Physical Verification Signoff Solution

Pegasus Verification System

Cadence Design Systems

Pegasus Verification System - Cadence Design Systems

The Cadence® Pegasus® Verification System is a cloud-ready physical verification signoff solution, which enables engineers to deliver advanced-node integrated circuits (ICs) to market faster. The groundbreaking technology delivers up to 10X improved performance on DRC runs and reduces turnaround time from days to hours. The Pegasus system’s innovative architecture and native cloud processing provides an elastic and flexible computing environment. Customers can now achieve complete full-chip signoff DRC on advanced-node designs in a matter of hours, helping designers deliver products to market faster, or easily run multiple DRC signoff iterations, if needed, at the time of tapeout. The Pegasus system provides a massively parallel architecture. It is the first solution to combine a pipelined infrastructure with stream processing delivering near-linear scalability across 100s of CPUs. The Pegasus system’s gigascale technology enables full-chip signoff DRC in just a few hours versus days. As many designs continue to grow in complexity, the Pegasus system can scale to meet customers’ stringent time-to-market requirements.

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Verification Suite

Cadence Design Systems

Cadence Design Systems

Using the Cadence Verification Suite, you can reduce system integration time by up to 50%, accelerating intellectual property (IP) development, system-on-chip (SoC) integration, and concurrent hardware/software development. This verification suite is comprised of core engines, verification fabric technologies, and solutions spanning these technologies.

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Parallel Simulation Engine

RocketSim

Cadence Design Systems

RocketSim - Cadence Design Systems

Complementing compiled-code simulators, Cadence® RocketSim™ parallel simulation engine eliminates functional verification bottlenecks by speeding up simulation using commonly available multi-core servers. The engine is proven for register-transfer level (RTL) system on chip (SoC), gate-level functional simulation, and gate-level design for test (DFT) simulation in numerous marquee systems and semiconductor companies in the mobile, server, and graphics domains. Ever-growing chip density and complexity slow down simulation, making functional verification a severe bottleneck. As a result, chip design projects miss their time-to-market targets, or designers end up taping out early with less confidence. RocketSim parallel simulation engine solves the bottleneck common in existing compiled-code simulators by offloading the time-consuming calculations to an ultrafast multi-core engine.