PCI Card with input channels

PCI_LVDS_8R - Dynamic Engineering (Dynamic Engineering)

The PCI_LVDS_8R has 8 channels of LVDS input. The channels are grouped two per Filter Xilinx. The input data is filtered, then written to the Input FIFO. There is one Input FIFO per LVDS channel. 1K x 32. One Latch Xilinx handles 4 LVDS channels. The data is read from the Input FIFO by the Latch Xilinx and either written to the SDRAM or the Output FIFO.