Showing results: 1 - 15 of 227 items found.
-
Mentor Graphics Corp.
Mentor Graphics provides best-in-class products for IC design. Calibre for physical verification, extraction, resolution enhancement and mask data preparation, ADVance MS for analog/mixed-signal simulation and an integrated tool flow for custom IC design
-
ALINT-PRO -
Aldec, Inc.
ALINT-PRO™ is a design verification solution for RTL code written in VHDL, Verilog, and SystemVerilog, which is focused on verifying coding style and naming conventions, RTL and post-synthesis simulation mismatches, smooth and optimal synthesis, correct FSM descriptions, avoiding problems on further design stages, clocks and reset tree issues, CDC, RDC, DFT, and coding for portability and reuse. The solution performs static analysis based on RTL and SDC™ source files uncovering critical design issues early in the design cycle, which in turn reduces design signoff time dramatically. Running ALINT-PRO before the RTL simulation and logic synthesis phases prevents design issues spreading into the downstream stages of design flow and reduces the number of iterations required to finish the design.
-
Jupiter 310 -
Averna
Jupiter is the industry standard for automated DOCSIS physical (PHY) layer testing. It provides the most comprehensive test coverage and accurate results on the market for DOCSIS 3.1 devices.
-
DVinsight -
Agnisys, Inc.
DVinsight-Pro is a Integrated Development Environment (IDE) for creation of Universal Verification Methodology (UVM) based System Verilog (SV) Design Verification (DV) code. Design & Verification Engineers can create correct by construction DV code because DVinsight-Pro is a design verification editor checker that provides helpful insight into user code and ensures compliance with UVM best practices while adhering to established standards.
-
Starter Kit - ETX -
ADLINK Technology Inc.
*ETX module of choice*CPU, Memory of choice*Thermal Solution (heatspreader, and heatsink) of choice*Reference Carrier Board*Schematics, Design Guide, and User ManualsADLINK USB Stick with Documentation, Software,
-
COM Express Type 6 Starter Kit Plus -
ADLINK Technology Inc.
The Type 6 Starter Kit Plus consists of a COM Express Type 6 module with ATX size Type 6 reference carrier board that offers one PCI Express x16 slot with proprietary pinout for DDI adapter card that convert DDI signal to DP or HDMI signal, one PCI Express graphics x16 slot, one PCI Express x4 slot, three PCI Express x1 slots, Serial ATA, VGA, LVDS, USB3.0/2.0, Gigabit LAN and Super I/O. All necessary cables are included.
-
Mentor Graphics Corp.
The Mentor Graphics Scalable Verification" is the most comprehensive EDA solution for functional verification, merging standards support, tools and a "design for verification" methodology to minimize verification cycles and costly design respins.
-
DIADIM -
PASI srl
Design and verifications of sheet-piles and bulkheads.
-
GreenPoint® -
ON Semiconductor
The GreenPoint Design Simulation Tool is an interactive online design and verification tool to help you generate and validate an electronic design. The simulation module provides an interactive design and verification environment. The power analysis module provides an interactive environment to analyze the performance of intelligent power modules (IPMs). The Phase Noise Explorer module enables an interactive environment for advanced phase noise/jitter analysis of clock tree designs.
-
SmartDV Technologies India Private Limited
We develop Verification Components, leveraging our rich experience in ASIC / SoC design verification and capabilities on high-level verification languages (HVLs). Our verification components are configurable, reusable plug-and-play verification solutions for standard interfaces based on HVL. We currently support SystemVerilog, Vera, SystemC, Specman E and Verilog. All our VIP''s are supported natively in SystemVerilog VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env.
-
ARV -
Agnisys, Inc.
Register verification is a significant part of the design verification problem. It is one of the first aspects of the design that must be tested because the rest of the semiconductor functionality depends on the accuracy of the register implementation. That is because registers contain the configuration setting of the hardware and is the basis of the hardware / software interface. ARV helps to auto generate UVM test-bench bus agents, monitors, drivers, adaptors, predictors, sequencers and sequences helps user to complete the verification right at first time.
-
Voyager M310e -
Teledyne LeCroy
The Voyager M310e is Teledyne LeCroy's flagship USB protocol verification system designed for USB 2.0, USB 3.2, Type-C, and USB Power Delivery. Offering the industry's highest fidelity probe design, flexible traffic generation, and a range of turnkey Compliance packages, the Voyager M310e is the most complete platform for cradle-to-grave USB design verification.
-
Silvaco Data Systems
Silvaco offer a full IC-CAD design flow including design capture, circuit simulation, layout design, physical verification, parasitic extraction and reduction, and post-layout analysis including statistical variation, IR-drop/EM.
-
Hiller Measurements
Surveyor – ESS is a resistance-monitoring, event-detection suite of tools specifically designed for standards-based design verification test applications, including:
-
Keysight Technologies
GoldenGate RFIC Simulation and Analysis Software is an advanced simulation and analysis solution for integrated mixed signal RFIC designs that is fully integrated into the Cadence Analog Design Environment (ADE). GoldenGate is part of Keysight's RFIC simulation, analysis and verification solution that also includes Momentum for 3-D planar electromagnetic simulation, SystemVue & Ptolemy wireless test benches for system-level verification, and the Advanced Design System (ADS) Data Display for advanced data analysis. This suite links the RF system, subsystem, and component-level design and analysis as part of a unique and comprehensive RFIC design flow.